The operation of a processor's (e.g., CPU's) physical interface in an advanced memory sub-system often involves the use of multiple clocks running at different speeds. In particular, the memory sub-system may be required to propagate data over a high-speed serializer/deserializer (serdes) link, operating at 6.4 gigabytes per second (Gb/s) or greater, but may also be required to interface with the traditional double data rate three (DDR3) memory around the much slower 1.6 Gb/s. Although slower, DDR3 memory (e.g., dynamic random access memory (DRAM), synchronous DRAM (SDRAM) and the like) adds the complexity of data bus bursts, where each burst may be directed at a different memory dual inline memory module (DIMM) or rank on a DIMM, each of which requires a different phase shift of the data output from the CPU in order to meet the input timing requirements at the DRAM to which the burst is targeted.
Typical memory modules are organized as either 64 or 72 bit-wide words. The depth and width of the module define the total density of the DIMM. For example, a 128 Mbyte wide×72 bit width is a 1 GB DIMM (128 M×8=1 GB). The configuration and density of the components used on a module define the number of ranks.
Each single rank on a module forms an identical arrangement of memory components to the other ranks. The term “rank” evolved from the need to distinguish the number of memory banks on a module as opposed to the number of memory banks on a component. So, “rank” is used when referring to modules, and “bank” is used when referring to components. The most commonly used modules have either a single rank of memory or a double rank of memory.
A DDR memory system requires a timing generator to provide a clock waveform meeting specific phase requirements to the I/O links of the memory (e.g., DRAM). The specific clock used for an output signal can be considered to meet requirements if using that clock for a transaction results in the memory receiving the transaction as intended, according to the standards defined by the Joint Electron Device Engineering Council (JEDEC) industry working group. The specific clock waveform used for an input signal can be considered to meet timing requirements if using that clock during a read transaction results in correctly sampling the intended data from the memory.
A timing generator may be required to create multiple different clock waveforms within a system at different points in time. These clocks could be differentiated by usage in output signals versus input signals, usage by a specific set of related I/O signals versus a different set of I/O signals, usage when addressing a different DIMM or a different rank on the same DIMM, or usage to meet the current timing requirements versus different requirements that the same piece of hardware may require in the future as parameters change in the memory.
In conventional systems, a delay-locked loop (DLL) running at the memory module (e.g., DDR3) frequency generates multiple output phases. During the phase switching operation between data bursts, a control system running at this same frequency stops the DLL's output, feeds in the new phase operation, and re-starts the DLL. Because this sequence is driven from a lower-speed clock, the duration of the phase switching is longer, causing pending data traffic to stall, which decreases the throughput of the memory subsystem, decreasing system performance.